At the physical layer, both SCL and SDA lines are of open-drain design, thus, pull-up resistors are needed. Pulling a line to ground signals a logic '0' and driving it high impedance to be pulled high signals a logic '1'. This wire-ANDing allows multiple nodes to connect to the bus without short circuits from signal contention. High speed systems (and some others) may use a current source pull-up on SCL or both SCL and SDA, to accommodate higher bus capacitance and enables faster rise times.
An important consequence of this is that multiple nodes may be driving the lines simultaneously. If any node is driving the line low, it will be low. Nodes that are trying to transmit a logical one (i.e. letting the line float high) can detect this and conclude that another node is active at the same time.
When used on SCL, this is called clock stretching and used as a flow control mechanism for slaves. When used on SDA, this is called arbitration and ensures there is only one transmitter at a time.
When idle, both lines are high. To start a transaction, SDA is pulled low while SCL remains high. Releasing SDA to float high again would be a stop marker, signaling the end of a bus transaction. Although legal, this is typically pointless immediately after a start, so the next step is to pull SCL low.
Except for the start and stop signals, the SDA line only changes while the clock is low; transmitting a data bit consists of pulsing the clock line high while holding the data line steady at the desired level.