The three shift registers are connected to form one 12-bit shift register. When x 1, S0 1, and S1 0, making the registers shift right. A 1 is shifted into the leftmost bit. When x 0, the register shifts left, loading 0’s from the right. After the input has been 0 for several clocks (or if the shift register is cleared), all bits will be 0. The output is 1 whenever there
is a 1 in the left bit of the shift register and x is 0. Note that if there are more than 12 consecutive 1 inputs, the shift register will contain all 1’s. When the input goes to 0, the output will be 1 for 12 clock times. Thus, this solution handles the situation where there are more 1 inputs than the register can hold (similar to the second counter design).