to the placement constraints, it is more desirable to consider
routing during placement because a bad routing may induce
unwanted effects and deteriorate layout quality. Since routing
is greatly affected by placement results, layout quality can be
enhanced if routing effects are considered in advance during
the placement phase.
Due to the continuous scaling of process technologies,
more and more circuits can be integrated into a single chip.
This increases functionality in modem chips; however, the
routing and power consumption become more serious
problems. The increasing complexity in routing not only raises
the chance of signal coupling but also make routing
congestion more severe. Since analog circuits are very
sensitive to noisy signals, we have better to place them away
from the noisy signals to reduce coupling effects. However,
routing is greatly affected by placement results. The better
way to eliminate congestion is to consider routability during
placement. Besides, resistors are gradually replaced by
switched-capacitors in modem analog integrated circuits for
lower power consumption. To achieve correct analog
functions, the capacitors must follow predefined capacitance
ratios. Capacitors should be placed in common-centroid layout
structure and distributed uniformly throughout the layout to
guarantee accurate capacitance ratios after integrated-circuit
fabrication. However, this placement style for capacitors may
result in large routing area. Therefore, the issue of routing area
needs to be considered during capacitor placement.
Above illustrations show several routing effects should be
considered during placement to enhance layout quality. The
following sections give an overview of the solutions for these
issues. In Section II, we show how to eliminate undesirable
coupling effect induced from specific nets during placement.
Then, the congestion elimination by placement expansion is
discussed in Section III. Section IV describes how to handle
common-centroid placements with the consideration of routing
area for capacitor arrays. Finally, Section V summarizes the
main conclusions of this paper.
II. SYMMETRY ISLAND CONSIDERING BOUNDARY
CONSTRAINT
In this section, we first demonstrate the situation that
analog devices in a symmetry group are affected by noisy
signals, and then show how to avoid this condition during
placement.
In analog and mixed-signal design, circuit performances
are sensitive to the parasitic mismatches caused by process
variation or thermal gradient. To reduce unwanted parasitic
mismatches and improve circuit performances, designers
usually place matched devices symmetrically in a layout [10,
11]. In order to obtain better matching, they also place the
matched devices belonging to the same sub-circuit close to
each other, in which a symmetry group is formed. Thus, Lin
and Lin [5] introduced the concept of symmetry islands for
symmetry groups and presented ASF-B*-trees [5] to ensure