We describe attestation protocols for three classes of secure
software-hardware architectures in Figure 1, based on three very
different threat models. In the first class, both the hypervisor and
the guest OS are trusted. In the second class, only the hypervisor
is trusted, while in the third class, only the OS is trusted. In the
first class, we use the remote attestation protocol defined for the
Trusted Platform Module (TPM) [1]. In the second and third classes
of architectures, we do not need a separate TPM chip but instead
use processor-based attestation. New ideas such as a layer-skipping
trust chain are used to enable more focused remote attestation reports
for guiding decisions on whether specific tasks can run securely on
remote systems, thus increasing the resilience of distributed systems.
We show how to model and verify the attestation protocol used with
an external TPM chip as a baseline. We then present streamlined
protocols for the two new and interesting classes of untrusted OS and
untrusted hypervisor architecture. We do not model the fourth class
of architectures where both the hypervisor and the OS are untrusted,
since no architecture has been proposed with that aggressive threat
model yet.