We defined another architecture which is composed of
three processors: Reneases processors (V850) where every
integrated core is just an image of the other. The
communication between them is assured by the use of a shared
memory where its address range is from 0x00000000 to
0x9fffffff. In this case, we consider one processor as a master
and the two others as slaves. The master writes a value in the
shared memory, gives the order to both slaves to do their tasks
and waits them to finish. Synchronization between processors
is ensured by flags.
We have also developed and tested several other
architectures that are composed of identical cores. In this way,
we insured that, by using OVPsim, we can instantiate any
number and type of identical cores with various architectural
choices.
B. Heterogeneous architectures with shared memory
OVP technology offers the possibility to make designs
composed of different IP cores. We present the simulation of
three heterogeneous architectures models.
We start by making a heterogeneous platform, the first
model, composed of an ARM7 and a MIPS32 processors, a
local memory for each core and a shared memory. The local
memory for both processors is from 0x00000000 to 0x9fffffff.
The shared memory is located from 0xa0000000 to 0xffffffff.
MIPS32 processor is a writer. Its application consists in
writing a number at the address 0xa0000000. The ARM7
processor is defined as a reader. Its application consists of
three tasks: Task 1 reads the written value, Task 2 calculates
the sum from 1 to the respective written number and Task 3
modifies the content of the address. Synchronization between
the processors is based on the algorithm of Peterson. Each
application should be cross-compiled for its target. For the
compilation as well as for the execution of the platform and
the application, we use the Minimal SYStem (MSYS). We can
get the number of executed instructions for both processors,
how components are connected and, at the end of the
simulation, a number of statistics is printed on the MSYS
window.
Figure 3 illustrates, the second model, the addition of
another type of processor: Renesas Processor (V850) to the
previous architecture.