The 4060 is a ripple counter so beware that glitches may occur in any logic gate systems connected to its outputs due to the slight delay before the later counter outputs respond to a clock pulse.
The count advances as the clock input becomes low (on the falling-edge), this is indicated by the bar over the clock label. This is the usual clock behaviour of ripple counters and it means a counter output can directly drive the clock input of the next counter in a chain. The clock can be driven directly, or connected to the internal oscillator (see below).
Output Qn is the nth stage of the counter, representing 2n, for example Q4 is 24 = 16 (1/16 of clock frequency) and Q14 is 214 = 16384 (1/16384 of clock frequency). Note that Q1-3 and Q11 are not available.
The reset input should be low for normal operation (counting). When high it resets the count to zero (all outputs low).
The 4060 includes an internal oscillator. The clock signal may be supplied in three ways:
From an external source to the clock input, as for a normal counter. In this case there should be no connections to external C and external R (pins 9 and 10).
RC oscillator as shown in the diagram. The oscillator drives the clock input with an approximate frequency f = 1/(2×R1×C) (it partly depends on the supply voltage). R1 should be at least 50k if the supply voltage is less than 7V. R2 should be between 2 and 10 times R1.
Crystal oscillator as shown in the diagram, note that there is no connection to pin 9. The 32768 Hz crystal will give a 2Hz signal at the last output, Q14.