3.3 Distributed Shared-Memory
The queues in IMs and OMs have to support parallel cell
arrivals and departures, which suggests the use of sharedmemory.
However, shared-memory is not scalable. In this
section, we propose a distributed shared-memory (DSM)
design to improve the scalability. The DSM distributes the
cells to distinct memory units in a memory bank, which
ensures that cells are mutually conflict-free with each other
on their departures. Similar technologies were previously
proposed (see, e.g., [41], [42], [43]). However, these architectures
require either memory speedup or use more memory
units. We use a buffered crossbar-based cell cache to eliminate
the memory speedup or to reduce the extra memory
units. In this section, we first introduce the DSM design in
IMs and OMs assuming that we have a high-speed cell cache
to temporarily store the arrived cells from input ports of an
IM/OM.