As we will see later, the communication between the computer and the FPGA
is the speed bottleneck of the whole system. For this reason we want to transfer
the minimum amount of data. In [1] only the nine pixels of the PW were stored in
the FPGA. Using this approach, after each slide of the PW, 3 new pixels were
red from the image and three pixels were forgotten. This means that after the
processing of the whole image each pixel was read three times and it represents
a lot or redundant transfers, but the register usage was small. If a 5 by 5 pixels
windows was used each pixel would be read ve times.
To avoid these redundant transfers we chose to per