Errata
CG1 Core Frequencies at or Below the DRAM DDR Frequency May Result in
Unpredictable System Behavior.
Problem: The Enhanced Intel SpeedStep® Technology can dynamically adjust the core operating
frequency to as low as 1200 MHz. Due to this erratum, under complex conditions and
when the cores are operating at or below the DRAM DDR frequency, unpredictable
system behavior may result.
Implication: Systems using Enhanced Intel SpeedStep Technology with DDR3-1333 or DDR3-1600
memory devices are subject to unpredictable system behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the affected steppings, see the Summary Tables of Changes.
CG2 Quad Rank DIMMs May Not be Properly Refreshed During IBT_OFF
Mode.
Problem: The Integrated Memory Controller incorporates a power savings mode known as
IBT_OFF (Input Buffer Termination disabled). Due to this erratum, Quad Rank DIMMs
may not be properly refreshed during IBT_OFF mode.
Implication: Use of IBT_OFF mode with Quad Rank DIMMs may result in unpredictable system
behavior.
Workaround: A BIOS workaround has been identified.
Status: For the affected steppings, see the Summary Tables of Changes.
CG3 PCIe* TPH Attributes May Result in Unpredictable System Behavior.
Problem: TPH (Transactions Processing Hints) are optional aids to optimize internal processing of
PCIe* transactions. Due to this erratum, certain transactions with TPH attributes may
be misdirected, resulting in unpredictable system behavior.
Implication: Use of the TPH feature may affect system stability.
Workaround: A BIOS workaround has been identified.
Status: For the affected steppings, see the Summary Tables of Changes.
CG4 PCIe* Rx Common Mode Return Loss is Not Meeting the Specification.
Problem: The PCIe* specification requires that the Rx Common Mode Return Loss in the range of
0.05 to 2.5 GHz must be limited to -6 dB. The processor’s PCIe* Rx do not meet this
requirement. The PCIe* Rx Common Mode Return at 500 MHz has been found to be
between -3.5 and -4 dB on a limited number of samples.
Implication: Intel has not observed any functional failures due to this erratum with any
commercially available PCIe* devices.
Workaround: None identified.
Problem: For the affected steppings, see the Summary Tables of Changes.