V. LOW-FREQUENCY MODELS
The modeling approach followed here has been proposed
in [1] and [8]. For frequencies much below the switching
frequency, a large-signal, low-frequency model of a NLC
controlled rectifier is shown in Fig. 10. The power absorbed by
the emulated resistance is transferred to the output through
the time-varying power source . This feature of the model
is common to all converters and control schemes that achieve
ideal resistive emulation at the input port. A unique aspect of
the NLC controlled rectifier is that the emulated resistance is
not only inversely proportional to the control input , but
is also directly proportional to the output voltage , even
without any external voltage-regulating feedback loop.
For the purpose of designing a slow voltage-regulating
feedback loop, the output side of the small-signal model can be
derived by averaging the current over a line cycle
(24)
Referring to Fig. 10, is the dc component of the current
and is the rms value of the input-line voltage. The
low-frequency small-signal model is obtained by linearizing
(24)
(25)
where the parameter values are given by
(26)
The resulting low-frequency small-signal model of the NLC
controlled rectifier is shown in Fig. 11. Note that the openloop
small-signal output resistance is two times lower than
in the rectifier with conventional power factor correction.
VI. EXPERIMENTAL VERIFICATION
A flyback rectifier with the NLC controller has been built
and tested. The experimental circuit is shown in Fig. 12. The
ac-line input is 85–130 Vrms, 60 Hz, and the output dc voltage
is regulated at Vdc. With a 1 1 transformer ,
this specifies the range of as
(27)
The switching frequency is kHz, and the transformer
magnetizing inductance is H. The maximum
load power is W, which corresponds to the load
parameter .
The output of the voltage-loop error amplifier built around
the opamp IC1 is the control voltage at the input of the
exponential NLC generator. The parameter is set by the time
constant , which is close to the
theoretical optimum value found in Section IV. The carrier
signal is the input of the voltage comparator IC3
The duty ratio of the clock signal CK is . At the
beginning of a switching period, the clock signal turns on the
switch to charge to and sets the FF IC4. The power
switch current is sensed using a current transformer CT with
turns ratio. The scaled switch current is integrated on
to obtain the signal at the input of the voltage
comparator IC3. The output of the FF IC4 controls the power
transistor . Fig. 13 shows experimental controller waveforms
during several switching cycles. All controller functions could
easily be implemented on a dedicated integrated circuit.
A simple voltage-regulating feedback loop has been designed
around the model of Fig. 11, as shown in Fig. 14. The
output voltage is scaled by the constant factor set by
and and subtracted from a constant reference voltage
set by . The difference is then passed through an error
amplifier with transfer function
(28)
where is the compensator zero frequency. The integral
compensation ensures zero steady-state error in the output dc