Architecture description languages (ADL) have been
introduced to help designers face the development
challenges that have arisen in the past few years, due
to the increasing complexity of modern architectures.
These difficulties have forced hardware architects and
software engineers to reconsider how designs are specified,
partitioned and verified. As a consequence, designers
are starting to move from hardware description
languages (VHDL, Verilog) and also beyond the RTL
level of abstraction toward the so called system level
design, where a tool for evaluating a new designed instruction
set architecture, which automatically generates
a software toolkit composed of assemblers, simulators,
etc is mandatory. Such tools are commonly
based on an architecture description language.
Besides their application and well known suitability
for designing and experimenting with new architectures
in the industry, architecture description languages
can be very useful for academic purposes, like
teaching/researching computer architecture at undergraduate
and graduate level. On one hand, at the
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undergraduate level, models of well known architectures
are appropriate to learn how a pipelined architecture
works, including interlocking, hazard detection
and register forwarding. If allowed by the ADL,
this model can be plugged to different memory hierarchies
in order to illustrate how the performance of
a given application can vary, depending on the choice
made for cache size, policy, associativity, etc. On the
other hand, at the graduate level, researchers can use
ADLs to model modern architectures and experiment
with their ISA and structure with all the flexibility demanded
in research projects. This paper is focused on
the application of an ADL in a computer architecture
course.