To enforce zero steady-state error, use integral control of the form
C(s) = K/s
where K is to be determined.
To determine the gain K, you can use the root locus technique applied to the open-loop 1/s * transfer(Va->w):
Click on the curves to read the gain values and related info. A reasonable choice here is K = 5. Note that the SISO Design Tool offers an integrated GUI to perform such designs (help sisotool for details).
Compare this new design with the initial feedforward design on the same test case