Today’s VLSI technology makes it both feasible and eco-
nomical to integrate a complex system on a single chip. De-
signing such a system on a chip (SoC) usually involves stitch-
ing pre-designed IP cores together through various forms of
communication links. As the delay of global interconnects be-
comes the dominating factor of system performance, the de-
sign of high performance global communication architectures
becomes the key to successful SoC designs.