Nowadays the digital systems design is almost
exclusively realized using hardware description languages
(HDL). In Europe, the VHDL (Very-High-Speed Integrated
Circuits HDL) is the most widely used HDL. Although HDLs
brought a lot of advantages into the design process, the HDL
structural models, especially on register transfer and lower
layers, are harder to read than the previously used schematic
representations. That is why a lot of commercial EDA (Electronic
Design Automation) systems include some kind of visualization
tool enabling to represent a model structure in a graphical form.
However, these systems are usually too complex and expensive
for the education purpose. In this case simple, easy to use
visualization tool would be more appropriate. The paper deals
with the problem of the structural models visualization as well as
with the design and implementation of the visualization tool
devoted to the VHDL structural models visualization. The
presented tool offers the possibility to display the schematic view
corresponding to the input VHDL model, edit the schematic
layout, print it or export it to an image file. The tool preserves the
model hierarchy and enables to easily switch among the
respective levels. It represents an useful tool in the process of the
VHDL structural model verification and debugging as well as for
documentation purposes.