hough Moore’s law continues to provide increasing transistor counts, the limited
on-chip power budget restricts the percentage of active transistors [Venkatesh et al.
2010; Esmaeilzadeh et al. 2011; Taylor 2012; Goulding-Hotta et al. 2012; Allred et al.
2012]. In recent years, an increasing percentage of those transistors are invested in the
large last-level caches (LLCs) utilized to bridge the gap between fast CPU cores and
slow off-chip memory accesses. Specifically, LLCs occupy as much as 50% of the chip
area and contribute to a significant amount of the chip’s leakage power [Kurd et al.
2010; Naffziger et al. 2006; Wendel et al. 2010; Wilkerson et al. 2010]. As shown in
Figure 1, a 16MB LLC consumes about 27% of on-chip power in a 16-core system, with
leakage power dominating the LLC’s power consumption. Hence, managing the power
consumption of LLCs has become an important design issue for future CMPs.