An examination of the high frequency loop,
shown in Fig 2, reveals parasitic inductances,
Ld(SW),Ls(SW),Ld(SR),Ls(SR), that play a crucial role in
determining the transition time. Thus, the goal of any layout
is to minimize these parasitic inductances so that they play a
minimal role in transition times. Two designs based on a one
switch and two synchronous rectifiers will be investigated.
Design 1 is a 2 layer, 62 mil board with 2-oz copper layers
and with the synchronous rectifiers placed as closely to each
other as possible. Design 2 is a 6-layer, 31 mil board with
2-oz outer copper layers and 1-oz inner layers.
A. Design 1
Design 1 is configured to have the input capacitors as
physically close as possible to the EPC 2015 switch device.
B. Design 2
III. RESULTS
A 12-1 V synchronous buck converter has been designed
utilizing three EPC 2015 eGaN enhancement mode HEMTs.
The converter is arranged with one high side switch and two
paralleled synchronous rectifiers. This combination has been
tested with two different layouts to see the effects of parasitic
inductance on the switching speed of the eGaN HEMTs. In the
first layout, the devices are arranged to minimize the layout
area. The layout is shown in Figure III. The maximum distance
along the ground return path is 15 mm. In the second layout,
the HEMTs are arranged in a line with enough space between