gorithm, where each row corresponds to a particular ratio, and
each entry in the row describes the margin for that particular
slow clock cycle
. Since the intent is to try to equalize setup and
hold time margins, the obvious choice is to use the same sync
pulse for data transfer in both directions. This has two effects:
1) the number of distributed pulses is halved, and 2) the anal-
ysis for determining setup/hold margin needs to be performed
in only one direction. Because of the symmetry and periodicity,
the worst case margin across both tables becomes
exactly
the
same.
A fallout from this sync pulse scheme is that for static timing
analysis (STA) performed at CMP frequency of 1.4 GHz, the
domain crossing timing path is speci
fi
ed as a multi-cycle path
with one CMP cycle (
714 ps @ 1.4 GHz) for setup/hold. The
STA tools easily handle constraints speci
fi
ed in this manner.