Fig. 10 shows the Niagara2 Crossbar (CCX). CCX serves as
a high bandwidth interface between the eight SPARC Cores,
shown on top, and the eight L2 cache banks, and the noncacheable
unit (NCU) shown at the bottom. CCX consists of two
blocks: PCX and CPX. PCX (“Processor-to-Cache-Transfer”)
is a 8-input 9-output multiplexer (mux). It transfers data from
the eight SPARC cores to the eight L2 cache banks and the
NCU. Likewise, CPX (“Cache-to-Processor Transfer”) is a