A metal loop stamped [I] into the lead frame provides a
5mV full scale signal at room temperature. In addition to
low offset sensitivity, the low signal level requires a low
noise system. Figure 2 shows a system level block diagram.
A delta sigma A/D converter was chosen because of the
filtering property of the decimation filter. In addition to
reducing quantization noise, the decimation filter will also
reduce out of band circuit noise. Chopping the delta sigma
modulator provides a result insensitive to circuit offset. The
temperature coefficient of the metal loop is corrected by
matching the temperature coefficient of the reference to that
of the metal loop. Taking advantage of a low cost EEPROM
process allows for digital trimming of the metal loop
manufacturing tolerance, including any kelvin connection
error. An extra bit of EEPROM allows a single die to
provide 1 amp full scale or 7 amp full scale current. A PWM
output provides a digital result of the sign and magnitude of
the current.
Two digital blocks, A/D result and Digital I/O, provide the
decimation filter for the delta sigma modulator, state
machine timing, test functions, EEPROM, and PWM
generation. The pulse density output of the delta sigma is
digitally filtered using a 1st order sinc function [2] to
provide a digital result proportional to current. The digital
result is compared to a digital ramp generator to create the
PWM output.