that it is both functionally correct and performs well. A large range of test
cases must be explored while many configurations are compared to optimize
the design. As microprocessors become more complex, encompassing both a
larger number of transistors and numerous architectural features for increased
performance, the design space that must be evaluated through simulation
explodes.
In the design of parallel systems, simulation times are increased further
by the need to simulate multiple processors, a still wider range of inputs, and
larger datasets. One technique for reducing the simulation time is to scale
datasets down in size [Culler and Singh 1999], but this approach introduces inaccuracies
and necessitates a detailed analysis of each workload to determine
which part(s) can be safely scaled. Another performance enhancement involves
simplified processor models with an emphasis on accurate memory subsystem
and interconnect simulation [Mukherjee et al. 2000]. However, these simplified
models do not reflect the behavior of modern superscalar, out-of-order processors.
A third method to address simulation explosion is to make use of parallel
simulation.
that it is both functionally correct and performs well. A large range of test
cases must be explored while many configurations are compared to optimize
the design. As microprocessors become more complex, encompassing both a
larger number of transistors and numerous architectural features for increased
performance, the design space that must be evaluated through simulation
explodes.
In the design of parallel systems, simulation times are increased further
by the need to simulate multiple processors, a still wider range of inputs, and
larger datasets. One technique for reducing the simulation time is to scale
datasets down in size [Culler and Singh 1999], but this approach introduces inaccuracies
and necessitates a detailed analysis of each workload to determine
which part(s) can be safely scaled. Another performance enhancement involves
simplified processor models with an emphasis on accurate memory subsystem
and interconnect simulation [Mukherjee et al. 2000]. However, these simplified
models do not reflect the behavior of modern superscalar, out-of-order processors.
A third method to address simulation explosion is to make use of parallel
simulation.
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