Individual flip flops almost always have both outputs. However, when
several flip flops are contained in one integrated circuit package, pin
limitations may make only the uncomplemented output available.
A simple SR master/slave flip flop can be constructed with two
gated latches, as shown in Figure 6.7. When the clock is 1, the S and R
inputs establish the values for the first flip flop, the master. During that
time, the slave is not enabled. As soon as the clock goes to 0, the master
is disabled and the slave enabled. The values of the master’s outputs, X
and X, are determined by the value of S and R just before the trailing
edge. These are the inputs of the slave. Thus, the slave (and the flip flop
output) changes as the clock goes to 0 (on the trailing edge) and remains
that way until the next clock cycle. We could get a leading-edge triggered
flip flop by connecting the clock to the slave and its complement to the
master. The change in the output of the flip flop is delayed from the edge
of the clock (a somewhat longer delay than that through a gate). Commercial
flip flops use a more complex but faster circuit.
We will concentrate on two types of flip flops, the D and the JK. The
D flip flop is the most straightforward and is commonly found in programmable
logic devices (Chapter 8). The JK flip flop almost always
produces the simplest combinational logic. We will also introduce the SR
and T flip flops, in between the discussion of the D and JK, since they
naturally lead to the JK.