Consistency, a common class of consistency models that
includes Intel IA-32 (x86). PSO is a SPARC-specific
consistency model that relaxes TSO by allowing reorderings between stores. RMO is a variant of Weak Consistency that is similar to the consistency models for
PowerPC and Alpha. DVMC enables switching between
models by using three ordering tables (Table 2-Table 4).
Atomic read-modify-write operations (e.g., swap) must
satisfy ordering requirements for both store and load.
SPARC v9 also features a flexible memory barrier
instruction (Membar) that allows exact specification of
operation order in a 4-bit mask. The bitmask contains
one bit for load-load (LL), load-store (LS), store-load
(SL), and store-store (SS) ordering. To incorporate such
membars, Table 4’s entries in the Membar rows and columns contain masks instead of boolean values. A boolean value is obtained from the mask by computing the
logical AND between the mask in the instruction and the
mask in the table. If the result is non-zero, ordering is
required.