Binary Counter
The design of a synchronous binary counter is so simple that there is no need to go through a sequential logic design process. In a synchronous binary counter. the flip-flop in the least significam
position is complemented with every pulse. A flip-flop in any other position is complemented
when all the bits in the lower significant positions arc equal to I . For example. if
the present state of a four-bit counter is A3A2AtAo ::: 00 11 . the next count is 0100. A o is always
complemented. AI is complemented because the present state of A o ::: I . A2 is complemented
because the present Slate of Al Ao ::: I I. Howe ver. A3 is not complemented. because
the present state of A2A] AO ::: 0 11. which does not give an a11- I 's condition.
Synchronous binary counters have a regular pattern and can be constructed with complementing flip-flops and gates . The regular pattern can be seen from the four-bit counter depicted in Fig. 6.12. The C inputs of all flip-flops are connected to a common clock . The counter is
enabled with the count enable input. If the enable input is O. all j and K inputs arc equal to 0