Most FPGA implementations of shortest-path algorithms reported in the literature conform to one of the following approaches. The first approach [11–13] is based on the idea that since graphs naturally correspond to circuits, it is beneficial to construct a circuit that resembles the graph topology. Babb et al. [11] describe a compilation technique that accepts a topological representation of a specific user input graph instance and generates a circuit that resembles the graph such that nodes correspond to logic and links correspond to wires. The circuit facilitates the computation of shortest paths by implementing logic based on the Bellman–Ford algorithm. However, this circuit representation of the graph is static and as stated earlier, any change in the input graph will require expensive recompilation and reconfiguration.