This accomplishes two things. The shift register is now leading-edge triggered (since the leading edge of the clock is the trailing edge of the flip flop input). Also, the clock input signal only goes to the NOT gate. Thus, this circuit presents a load of 1 to the clock, rather than a load of 4 (if the signal went to all four flip flops). When a trailing-edge triggered shift register is desired, a second NOT gate is added in series with the one shown. Sometimes, the x input is first inverted to present only a load of 1. Both of these changes are shown in the circuit of Figure 8.3.