The simplest approach is to provide two address fields in each microinstruction.
Figure 16.6 suggests how this information is to be used. A multiplexer is provided
that serves as a destination for both address fields plus the instruction register.
Based on an address-selection input, the multiplexer transmits either the opcode or
one of the two addresses to the control address register (CAR).The CAR is subsequently
decoded to produce the next microinstruction address.The address-selection
signals are provided by a branch logic module whose input consists of control unit
flags plus bits from the control portion of the microinstruction.