a) There needs to be a co-incident or reference edge from
which sync pulses can be generated. Thus, for a 2.75:1
ratio, the CMP clock rising edge would align with the DR
clock edge every 11 CMP or 4 DR cycles.
b) Clock edges which coincide nominally at the source
will have moved apart at the destination. Therefore,
pll_cmp_clk–pll_dr_clk phase alignment at the PLL