The detected edges are displayed by combining the horizontal and vertical edges "(1) ." This paper proposes a hardware architecture of Prewitt edge detection. The input image is limited to 8-bit grayscale and a frame size of 256 x 256 pixels. Moving window is limited to 3 x 3 masks. The architecture is targeted for AItera FPGA using Quartus II and is capable of operating with a clock frequency of 145 MHz at 550 frames per second (fps). Verification is through synthesis only with parameters obtained from simulation on Matlab. By using the combination of both MatIab and Veri log, it can be easily import and export data to the designed hardware implementation to read and display images.
II. RELATED WORKS Alzahrani and Chen [2] proposed a pipeline architecture which is capable of producing one edge detected pixel for every clock cycle with maximum clock frequency of 10 MHz. The architecture is operational for real time edge detection application. Shen et al. [3] presented a software implementation of Perwitt edge detection technique by using convolution operation. The scheme is capable of performing on compressed images and videos that can be used in variety of image processing application for instance motion estimation and comer detection. Pel-Yung [4] proposed the systolic array architecture with scalable first in, first out (FIFO) design to perform the effect of edge detection on five images with different size. It is capable to produce 73.6 MHz frequency with video rate 280 fps. Abbasi et al [5] proposed a real time architecture for Perwitt edge detection by conducting pipelining technique. The architecture executed faster than the software designed version by C or C++ languages.
III. THE PROPOSED HARDWARE ARCHITECTURE OF PREWITT EDGE DETECTION The proposed architecture is divided into two parts, the data path unit (DU) and the control unit (CU). Fig. 2 displays the top-level view of the proposed hardware architecture for Prewitt edge detection. A 64 K bytes external memory device is used to store the image pixel values. First, MatIab software read the raw image pixels and stores it into a memory initialization file (mit). Fig. 3 shows the architecture design of the memory pointer unit (MPU), extemal memory and delay line.