DRAMs are one of the main players of computer system
energy consumption due to their large capacities and
frequent accesses. Consequently, many schemes have
been proposed to reduce DRAM power/energy consumption.
Some of them propose new DRAM system and chip
organizations, which are effective in reducing power consumption
but intrusive. In contrast, we minimize DRAM
write accesses at chip level with minimal modification of
the conventional DRAM system organization and small addition
to caches. When all data going to the same DRAM
chips are not modified, the chips are not accessed. Consequently,
chips are accessed selectively in our scheme
while all chips are accessed simultaneously in the conventional
DRAM system. Our chip-based selective DRAM
write scheme is shown to reduce DRAM power and energy
consumptions by 17% and 14%, respectively, on average.
The overheads of our scheme are small in terms of performance,
area, and energy consumption