ABSTRACT
This paper describes the architecture and physical design of the
AMD Bobcat x86 microprocessor core-C6 (CC6) sleep state.
Each core and dedicated 512KB L2 cache use control flows to
save and restore the x86 architectural state in concert with a
network of PFET sleep transistors that drive an internal voltage
domain. Measured results show an approximate 92% reduction in
leakage power at the cost of 1-3% die area with a 31μs restore
latency. Each core and L2 cache pair use 98cm of total
transistor width in a TSMC 40nm bulk CMOS process.