The area between source and drain beneath the gate, channel 'has length of L and width of W; it is where the inversion
layer is formed when sufficient voltage is biased to the gate
and drain which then tum on the MOSFETs. The oxide layer
with certain thickness, tox, separate the gate and the channel.
According to [9],L and to x of 35 nm and 1.2 nm,respectively,
have been demonstrated in 65 nm technology node