The common ULSI system design objectives are such as improving or maximizing wiring ability, reliability and/or yield, and reducing or minimizing chip size, power consumption, crosstalk, and coupling noise. Circuit layout is the process of placing and interconnecting a set of modules as specified by a connection of multiterminal nets. These are crucial factors in designing next generation EDA (Electronic Design Automation) tools. In this research paper, we consider two system design objectives which are wiring length and crosstalk minimization. This paper present a new row-based floorplan and routing suitable for different design styles. We propose methodologies and directions for floorplan and routing design automation tools to meet the challenges ahead with Simulated Annealing (SA) approach in floorplan and routing process. This approach is one of the efficient heuristic search algorithms to effectively predict and optimize various design objectives.