Electrode fabrication
Gold electrode chips were fabricated on 100 mm (100) silicon
wafers wet oxidized at 1050 C for 1.5 h to form 500 nm of SiO2
as an electrical insulating layer. Standard UV lithography and liftoff
processes were used to pattern the 300 nm Au on 10 nm Ti electrode
layer deposited by electron-beam evaporation. A 500 nm
PECVD silicon nitride layer was deposited using a STS PECVD reactor.
A second UV lithography step followed by a SF6 and O2 STS RIE
plasma etch defined the 1 mm2 electrode and 3 mm by 2 mm clip
contact pad openings in the nitride layer. Acetone removed the
bulk of the resist and a 10 min plasma ashing step removed residual
resist. Finally, the wafers were removed from the clean room for
dicing.