Although the scaling of CMOS transistors has past through
some 'brick wall" predictions as reported in [4], pessimists
believe that it will finally reach the boundary at size of 22 nm
as forecasted in the International Technology and Roadmap
for Semiconductors ITRS 2007 [1], approximately at the end
of next decade. They frequently cite that CMOS transistors
are approaching atomistic and quantum mechanical physics
boundaries [5]. Furthermore, the concern is not only about
the inability of the devices itself to continue operate steadily
but also the constraints from the economic and technology
point of view.