There are several approaches to providing storage of critical data power-down situations. In one method, all critical data during normal system operation are stored in RAM that can be powered from backup batteries whenever power is interrupted. Some CMOS RAM chips have very low standby power requirements (as low as 0.5 mW) and are particularly well suited for this task. Some CMOS SRAMs actually include a small lithium battery right on chip. Of course, ever with their low power consumption, these CMOS RAMs will eventually drain the batteries is power is out for prolonged periods, and data be lost.
Another approach stores all critical system data in nonvolatile flash memory. This approach has the advantage of not requiring backup battery power, and so it presents no risk of data loss even for long power outages. Flash memory, however, cannot have its data changed as easily as static RAM. Recall that with a flash chip we cannot erase and write to one or two bytes, it must be done a sector at a time. This requires the CPU to have to rewrite a large block of data even when only a few bytes need to be changed.
In a third approach, the CPU stores all data in high-speed, volatile RAM during normal system operation. On power-down, the CPU executes a short power-down program (from ROM) that transfers critical data from the system into ether battery-backup CMOS RAM or nonvolatile and sends a signal to the CPU to tell it to begin executing the power-down sequence.
In any case, when power is turned back on, the CPU executes a power-up program (from ROM) that transfers the critical data from the backup storage memory to the system RAM so that the system can resume operation where it left off when power was interrupted.