ยาก In addition, portability is limited. The processors typically used in the deeply embedded 1 systems area do not pro-vide appropriate atomic CPU instructions, such as compare-and-swap or load-linked/store-conditional, to ease the im-plementation of wait-free synchronization. Instead, these instructions must be emulated using more fundamental and often very restricted atomic CPU instructions. This emu-lation means increased resource consumption in terms of CPU clock cycles and memory consumption which cannot always be tolerated.