The NFC-WISP is a credit card size PCB board with surface mount components on both sides (Figure 1). A block diagram of the NFC-WISP is shown in Figure 2. The coil antenna and tuning network feed the power harvesting block which rectifies the incoming RF energy into DC voltage to power the system. An optional high-density storage element in the form of a battery or super capacitor can be used for long-term storage of wireless power. The demodulator follows the envelope of the RF carrier wave to extract the amplitude shift-keyed 106kHz data stream from the NFC-RFID reader. This base-band waveform is read by the TI MSP430F5310 MCU and a 13.56MHz internal clock is used for data recovery. An additional low power and low
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UBICOMP/ISWC '15 ADJUNCT, SEPTEMBER 7–11, 2015, OSAKA, JAPAN
frequency 32.768kHz watch crystal is used to enable realtime clocking functionality with lower power cost. Up-link data is sent back to the reader from the tag via load modulation. On-board peripherals such as accelerometer and non-volatile FRAM are powered and managed by the MCU. Finally an option 2.7 inch or 2.0 inch E-ink screen can be used for user interface.