Figure 2. The root hierarchical screen shows, at the block level, how the
processor, memory, peripheral device controllers’ lines (KP1.x and KP2.x), and
DMA controllers’ line (DMA1.x) interconnect through the system bus. The
data (DBUS) and address bus (ABUS), appear in green if they are in the state
of high impedance; otherwise they appear gray with hexadecimal values. The
control bus lines (RDBUS, WRBUS, and FCBUS) appear in blue if the signal
has a logical value of zero; and red, if the value is one.