Instruction set orthogonality[edit]
See also: PDP-11 architecture
The PDP-11 processor architecture had a mostly orthogonal instruction set. For example, instead of instructions such as load and store, the PDP-11 had a move instruction for which either operand (source and destination) could be memory or register. There were no specific input or output instructions; the PDP-11 used memory-mapped I/O and so the same move instruction was used; orthogonality even enabled moving data directly from an input device to an output device. More complex instructions such as add likewise could have memory, register, input, or output as source or destination.
Most operands could apply any of eight addressing modes to eight registers. The addressing modes provided register, immediate, absolute, relative, deferred (indirect), and indexed addressing, and could specify autoincrementation
Instruction set orthogonality[edit]
See also: PDP-11 architecture
The PDP-11 processor architecture had a mostly orthogonal instruction set. For example, instead of instructions such as load and store, the PDP-11 had a move instruction for which either operand (source and destination) could be memory or register. There were no specific input or output instructions; the PDP-11 used memory-mapped I/O and so the same move instruction was used; orthogonality even enabled moving data directly from an input device to an output device. More complex instructions such as add likewise could have memory, register, input, or output as source or destination.
Most operands could apply any of eight addressing modes to eight registers. The addressing modes provided register, immediate, absolute, relative, deferred (indirect), and indexed addressing, and could specify autoincrementation
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