• Evaluation system
The evaluation system consists of a PC with two PCIe
slots to which the FPGAs, the data generator, and the
prototype front-end DAQ were attached. This system can
control the entire evaluation system, and some evaluation
information can also be read from the FPGA boards, such
as that of data consistency checks and bandwidths. All
communication between the FPGAs and the PC, such as
sending control cOlmnands, obtaining and setting FPGA
register information, and error handling, can be accomplished
via the PCIe bus. Data transmission between
the Prototype front-end DAQ and this system by using
PCIe is achieved with the help of direct memory access
(DMA).