As mentioned, the Cortex-M3 core includes a vectored interrupt controller (NVIC) (see Chapter 11 for more details). The NVIC is a programmable device that sits between the CM3 core and the micro-controller. The CortexM3 uses a prioritized vectored interrupt model – the vector table is defined to reside starting at memory location 0. The first 16 entries in this table are defined for all Cortex-M3 implementations while the remainder, up to 240, are implementation specific; for example the STM32F100 devices define 60 additional vectors. The NVIC supports dynamic redefinition of priorities with up to 256 priority levels – the STM32 supports only 16 priority levels. Two entries in the vector table are especially important: address 0 contains the address of the initial stack pointer and address 4 contains the address of the “reset handler” to be executed at boot time.
The NVIC also provides key system control registers including the System Timer (SysTick) that provides a regular timer interrupt. Provision forbuilt-in timer across the Cortex-M3 family has the significant advantage of making operating system code highly portable – all operating systems need at least one core timer for time-slicing. The registers used to control the NVIC are defined to reside at address 0xE000E000 and are defined by the Cortex-M3 specification. These registers are accessed with the system bus.
2.2 STM32 F1
The STM32 is a family of micro-controllers. The STM32 F1xx microcontrollers are based upon the Cortex-M3 and include the STM32F100 valueline micro-controller used on the discovery board considered in this book. The STM32 L1 series is derived from the STM32 F1 series but with reduced power consumption. The STM32 F2 series is also based upon the Cortex-M3 but has an enhanced set of peripherals and a faster processor core. Many of theeripherals of the STM32 F1 series are forward compatible, but not all. The STM32 F4 series of processors use the Cortex-M4 core which is a significant enhancement of the Cortex-M3. Finally, there is a new STM32 family – the STM32 F0 based upon the Cortex-M0. Each of these families – STM32F0, STM32 F1, STM32 L1. STM32 F2, and STM32 F4 are supported by different firmware libraries. While there is significant overlap between the families and their peripherals, there are also important differences. In this book we focus on the STM32 F1 family.
As illustrated in Figure 2.3, the STM32 F1 micro-controllers are based upon the Cortex-M3 core with a set of peripherals distributed across three buses – AHB and its two sub-buses APB1 and APB2. These peripherals are
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