A block diagram of the STM32F100 processor used on the value line
discovery board is illustrated in Figure 2.1. The Cortex-M3 CPU is shown in
the upper left corner. The value line components have a maximum frequency
of 24 MHz – other STM32 processors can support a 72 MHz clock. The
bulk of the figure illustrates the peripherals and their interconnection. The
discovery processor has 8K bytes of SRAM and 128K bytes of flash. There are
two peripheral communication buses – APB2 and APB1 supporting a wide
variety of peripherals.