Fig. 10 shows the Niagara2 Crossbar (CCX). CCX serves as
a high bandwidth interface between the eight SPARC Cores,
shown on top, and the eight L2 cache banks, and the noncacheable
unit (NCU) shown at the bottom. CCX consists of two
blocks: PCX and CPX. PCX (“Processor-to-Cache-Transfer”)
is a 8-input 9-output multiplexer (mux). It transfers data from
the eight SPARC cores to the eight L2 cache banks and the
NCU. Likewise, CPX (“Cache-to-Processor Transfer”) is a 9-input 8-output mux, and it transfers data in the reverse direction.
The PCX and CPX combined provide a Read/Write
bandwidth of 270 GB/s. All crossbar data transfer requests
are processed using a four-stage pipeline. The pipeline stages
are: Request, Arbitration, Selection, and Transmission. As can
be seen from the figure, there are possible
source destination pairs for each data transfer request. There is
a two-deep queue for each source–destination pair to hold data
transfer requests for that pair.