An analytical model for switching noise with an on-chip
bypass capacitor is presented. To incorporate various design
parameters into the model, a differential equation is formulated
and solved by Laplace transforms. Based on the model,
optimum on-chip capacitor size is determined and compared
with HSPICE simulation results. In the simulation, a realistic
0.6ym BSIM device model at bcst process conditions is used
and good corrclation is demonstrated.