We have shown that the Pull–Model approach for functional level simulation of digital logic circuits produces both correct and efficient simulations of a simple design such as the LC3. Compared to the more traditional method of forwarding events (pushing level changes) to output devices, our approach gives a speedup of a factor of nearly 80 in our experiments. In addition,the pull –model required zero events unlike traditional forwarding as seen in table I. We do not claim that this approach is universally applicable for either gate–level or functional–level logic simulations. Clearly, when speed–of– light delays between devices are important and being measured, a more detailed and less efficient approach must be employed. However, for experimenting with designs for logic