Usually, CMOS technology is characterized by three main parameters: the minimum lithographic length, the well doping type and the number of available polysilicon and metal interconnection layers. CMOS processes can be nwell,p-well or twin-tub. All experimental HV devices presented in this contribution are NMOS transistors.However, the fabrication of PMOS devices is also possible, with both n-well and p-well processes. On the other hand,the fabrication of PMOS devices in a twin-tub process could become a difficult or even impossible task, depending on foundry policy and on the versatility of mask generation and preparation.