2. Related work
Network-on-chip (NoC) architectures [5–10] have been proposed as a solution for the problem of on-chip communication in multi-tile SoC architectures. The architectures are presented as replacements of the on-chip time-division multiplex buses (e.g. the AMBA bus from ARM Inc. [11]).
All the proposed solutions are based on routers interconnected through network links. The solutions differentiate in the topology of the network and the implementation of the individual routers. The two dimensional mesh is the most common topology compared with other topologies such as hexagons, butterflies, tree or hypercube structures. The implementations for the routers vary widely using techniques of packet or circuit switching, dynamic or static scheduling, wormhole or virtual-cut through routing.
The majority of the current router implementations for network-on-chip are based on a packet-switched, synchronous networks [5–9]. Using known routing protocols the number of buffers are minimized and best-effort traffic can be served. In the circuit-switched solution [10] buffering is not necessary. To handle guaranteed throughput traffic several techniques are used, such as: contention free routing [5], static scheduling [10], virtual channels [6], virtual circuits [8] and priorities [9].
The routers are benchmarked using a local area network approach where the benchmarks use random traffic patterns. New (more specific) NoC benchmarks can be necessary, because the on-chip traffic patterns have other characteristics [12] and demands [13].
2. Related work
Network-on-chip (NoC) architectures [5–10] have been proposed as a solution for the problem of on-chip communication in multi-tile SoC architectures. The architectures are presented as replacements of the on-chip time-division multiplex buses (e.g. the AMBA bus from ARM Inc. [11]).
All the proposed solutions are based on routers interconnected through network links. The solutions differentiate in the topology of the network and the implementation of the individual routers. The two dimensional mesh is the most common topology compared with other topologies such as hexagons, butterflies, tree or hypercube structures. The implementations for the routers vary widely using techniques of packet or circuit switching, dynamic or static scheduling, wormhole or virtual-cut through routing.
The majority of the current router implementations for network-on-chip are based on a packet-switched, synchronous networks [5–9]. Using known routing protocols the number of buffers are minimized and best-effort traffic can be served. In the circuit-switched solution [10] buffering is not necessary. To handle guaranteed throughput traffic several techniques are used, such as: contention free routing [5], static scheduling [10], virtual channels [6], virtual circuits [8] and priorities [9].
The routers are benchmarked using a local area network approach where the benchmarks use random traffic patterns. New (more specific) NoC benchmarks can be necessary, because the on-chip traffic patterns have other characteristics [12] and demands [13].
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