TO AVOID closed-loop instability, frequency compensation
is necessary in opamp design [1]–[7]. For two-stage
CMOS opamp, the simplest compensation technique is to
connect a capacitor across the high gain stage. This results in
the pole splitting phenomena which improves the closed-loop
stability significantly. However, due to the feed-forward path
through the Miller capacitor, a right-half-plane (RHP) zero
is also created. In theory, such a zero can be nullified if the
compensation capacitor is connected in conjunction with either
a nullifying resistor or a common-gate current buffer (Fig. 1).
The design procedures of the former type of opamp have been
proposed, e.g., in [2] and more recently in [3]. However since
both the procedures in [2] and [3] employ pole–zero cancellation,
they are sensitive to process and temperature variation.
Although the implementation of the opamp with current
buffer compensation has been reported [4] and the design
strategy has been proposed [1], the complete design procedure
for the opamp of this type has never been presented. In this
paper, we attempt to fill the gap by proposing the design
procedure for the CMOS opamp with Miller compensation in
conjunction with the current buffer.
It should be pointed out that unlike the strategy proposed in
[1], which results in the opamp with a pair of complex conjugate
poles and one finite zero, the proposed design procedure
is based on the strategy which would theoretically result in the
opamp with only one real nondominant pole. The differences of
the closed-loop behavior between these two compensation conditions
will be considered in the next section.