Fig. 2 Designed and implemented floating point counter layout. In
order to run at high frequency and process data in floating point format,
the adder has to be a pipelined architecture. In the plot, a pipeline of 8
taps is supposed for example. In this case, MUX B initializes the
pipeline with 8 values equally spaced of 1 sampling interval TS. During
the first 8 clock cycles, MUX A feeds the adder with the 0 value and the
adder output ranges from TS to 8TS. After the first 8 clock cycles, the
adder sum the constant value 8TS from MUX A to the pipeline content
that is last 8 values of adder output.