The ZPU is a very small, 32-bit processor, advertised by
the developer Zylin as “the worlds smallest 32-bit CPU with
GCC toolchain” [14]. The hardware description is licensed
under a FreeBSD license and the software under the GNU
General Public License (GPL). Both license models offer
free redistribution and adaption of the sources, which is a
prerequisite for modifications of the design.
The architecture of one ZPU Core is shown in Figure 2.
It consists of only three main components: 1. The control
and execution unit Execute does the instruction execution and
address calculation; 2. The instruction decoder Decode x4
which fetches up to four instructions for decoding; 3. The stack
registers Stack A and Stack B where two words from the main
memory (Memory) stack are temporarily stored. The ZPU is a
stack-based architecture; apart from Stack A and Stack B the
ZPU has no further registers. Every calculation is done by first
fetching the appropriate words sequentially from the stack to
the registers and then executing the instruction. Afterwards the
result is written back to main memory. Although the internal
execution has several stages, no pipelining is present. This
simplifies the control logic because no hazards can occur